The present invention relates to a two-layered gate structure of a semiconductor device in which gates are structured into two layers, and a non-volatile storage element in which the structure is used. It also relates to a method for manufacturing the two-layered structure.
A conventional two-layered gate structure for a non-volatile storage element will now be described by way of example with reference to FIG. 1.
As shown in FIG. 1, an element isolation region 113 is formed on a peripheral surface of an element formation region 112 set in a semiconductor substrate 111. This element isolation region 113 is formed through a LOCOS method, and its top surface is raised from the surface of the semiconductor substrate 111.
Also, a first gate insulating layer 114 is formed on the top surface of the element formation region 112 of the semiconductor substrate 111. A first gate electrode (i.e., floating gate electrode) 115 is formed so as to overlap over a part of a top portion of the element isolation region 113.
A second gate insulating layer 116 is further formed on the top surface of the above-described first gate electrode 115. A second gate electrode (i.e., control gate electrode) 117 is formed so as to overlap over the first gate electrode 115 of the second gate insulating layer 116.
Also, source/drain regions (not shown) are formed on both sides of the first gate electrode 115.
The two-layered structure is formed in the semiconductor device 101 in the first conventional case as described above.
A method for producing the two-layered gate structure of the semiconductor device 101 will now be described with reference to FIGS. 2A to 2C in which the same reference numerals are used to designate the same components as shown in FIG. 1.
As shown in FIG. 2A, the element isolation region 113 is formed on the semiconductor substrate 111 in accordance with a LOCOS method. Subsequently, after a first insulating layer 121 has been formed on the element formation region 112, a first electrode formation layer 122 is formed over an entire top surface thereof.
Then, as shown in FIG. 2B, the first electrode formation layer 122 is patterned to form an electrode pattern 123 through a lithography and an etching technology. A second insulating layer 124 and a second electrode formation layer 125 are formed to cover the electrode pattern 123.
Thereafter, as shown in FIG. 2C, the second gate electrode 117 is formed by the second electrode formation layer 125 and the second gate insulating layer 116 is formed by the second insulating layer 124 in accordance with the lithography and the etching technology. Furthermore, the first gate electrode 115 is formed by the electrode pattern 123. Then, the first insulating layer becomes the first gate insulating layer 114.
However, as shown in FIG. 1, in the case where the two-layered gate structure of the semiconductor device 101 of the first conventional example is applied to a non-volatile memory device, for example, since both the upper end portions 115a and 115b of the first electrode 115 are sharply or angularly formed into edges, when a high voltage (of, for example, about 15 to 25V) is applied to the second gate electrode (i.e., control gate electrode) 117, an electric field will be concentrated on both the upper end portions 115a and 115b. As a result, electrons accumulated in the first gate electrode 115 will be removed. Since an amount of charge accumulated in the first gate electrode 115 is changed in case of such a phenomenon, an amount of memory information therein would be changed. Accordingly, it is safe to say that the data holding performance would be low in such a structure.
Also, in the method for producing the semiconductor device, after the first gate electrode has been formed by patterning the first electrode formation layer, the second gate insulating layer and the second gate electrode are formed to cover the first gate electrode in a gate width direction. For this reason, the second gate insulating layer and the second gate electrode are formed on the stepped portions formed in the first gate electrode.